Pulse processing circuits are widely used in data transmission systems, computers, and associated equipment. These circuits typically comprise active components of a given "logic family," for example, transistor-transistor logic (TTL), emitter-coupled logic (ECL), etc. Each logic family has its own features and operating characteristics, and while generally a particular logic family is utilized in a given processing circuit, it would sometimes be desirable for such a family to be compatible with other logic families. However, one major problem that makes such compatibility difficult is that different logic families have different operating speeds, and specifically, the minimum pulse width to which a logic family will completely respond is an operational limit.
Various pulse-stretching techniques have been utilized to provide pulse normalizers which stretch the output pulses from logic families having high-speed switching characteristics so that such output pulses are within the operational limits of logic families having low-speed switching characteristics. Such prior art pulse normalizers typically include RC or LC timing circuits. However, because the transfer functions of these circuits are exponential, inherent recovery or "memory" problems exist therein, resulting in erroneous or faulty manipulation of data. Further, separate circuits have been required for each positive and negative polarity inputs, resulting in matching errors. Another problem incurred by prior art pulse normalizers is that pulses which are wider than the minimum width required are also stretched, causing unpredictable operation.